1. Field of the Invention
This invention relates generally to the manufacture of integrated circuits using silicon technology, more particularly, to the vertical layering and layout design of metal contacts on the surface of a silicon junction.
As the design dimensions of MOS (Metal Oxide Semiconductors) transistors have been decreased to improve performance, conventional layout rules require smaller metal contact areas, smaller alignment tolerances of the metal to the junction area and more precise photoresist masking tolerances. The typical implementation of the self-aligned silicide processes for gate interconnect and transistor junction (source/drain) surfaces presents a plasma etch control problem. The self-aligned silicide process, commonly referred to as the salicide process, includes the deposition of a metal over the silicon surfaces of the transistor source and drain regions and over the poly-crystalline silicon surface of the gate interconnect regions. The metal layer then reacts with the silicon and poly-crystalline silicon surface at an elevated temperature (400.degree. C. to 800.degree. C.) to form a metal silicide, such as CoSi.sub.2 or TiSi.sub.2. The unreacted metal is then removed from the wafer surface, leaving the metal silicide over the source/drain regions and over the gate interconnect regions. Exceeding etch process tolerances at the contact etch step will result in the erosion of silicide layers (such as TiSi.sub.2, etc.). Photoresist masking and lithographic process variations in a manufacturing environment may prevent consistent definition of small contact areas required by small geometry, conventionally designed MOS transistors. Exceeding masking layer to layer alignment tolerances will result in etch erosion of the field oxide boundary around each transistor during plasma contact etch, ultimately resulting in transistor failure.
2. Description of the Related Art
In the article by D. C. Chen, et al., cited above as a related publication, a process is described that can achieve the same purpose, i.e. to provide a layer of material to protect a portion of the substrate against subsequent processing steps. The protective layer described in the reference is produced by the deposition of a layer of refractory metal and a layer of amorphous silicon. These two layers involve a procedure requiring a plurality of process steps. Furthermore, the deposition of the material layers are subject to strict controls to be successful. Finally, the described protective layer was useful only for a self-aligned silicide (salicide) process. These features minimize the usefulness of the protective layer described by Chen, et al.
A need has therefore been felt for a process that can provide a protective layer over a semiconductor junction in a silicon substrate that does not involve critical process control and which has a wide applicability to fabrication of semiconductor junctions.